Embedded Static Random Access Memories (SRAMs) are commonly utilized as cache memory in semiconductor devices such as microprocessors, and as general purpose memory in application-specific integrated circuits (ICs). These devices receive significant performance enhancement by having embedded memory arrays, as opposed to utilizing external memory devices, but at an expense such as die space. A typical die, for instance, may be configured with many embedded SRAM arrays. It is not uncommon for these, and other types of memory arrays, to include millions of addressable storage cells (bits) organized into rows and columns. The number of bits in each array increases the chances of a defective bit, and thus, the potential of a die being rendered unusable after fabrication. For this reason, manufacturing guidelines state that redundancy should be built into each memory array in order to maintain acceptable yield. Redundancy is primarily accomplished through each array having some number of spare rows and columns to replace faulty ones. This type of redundancy is typically referred to as random access memory (RAM) redundancy or redundant memory. Memory redundancy tends to increase array size to account for the spares, which is particularly problematic when there are numerous or unusually small or fragmented memory arrays embedded within a die. In some cases, such as when there are unusually small and/or fragmented arrays, the amount of space needed to accommodate spares, and by extension maintain yield, can exceed available die space. This increase in array size, in turn, enhances the probability of defect. Thus there are numerous tradeoffs associated with providing adequate amounts of embedded memories to meet die performance requirements while keeping manufacturing costs low through maintaining an acceptable yield.